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What does it take to move an Edge AI application from a simple prototype to an architecture that can run across different embedded platforms?

In this interactive live session, we will build and evolve a voice-controlled Edge AI application together with the audience. Starting with a voice recognition model, an embedded Linux device will recognize spoken color commands and use them to control a physical light in real time.

The audience will then become part of the AI development process. Using only their smartphones and a shared link, attendees will contribute voice samples for a new color, creating a real dataset during the session. We will use Edge Impulse to train the updated model and deploy it as part of a containerized application. By the end of the session, the device will recognize a command that did not exist when the presentation started.

While the model is being trained, we will explore the architecture behind the demo: Yocto and Embedded Linux, containers, AI runtimes, hardware access, drivers and acceleration. We will discuss what can be portable inside a container, what remains dependent on the underlying platform, and why these boundaries matter for long-term product development and maintenance.

The same application will be shown on the Arduino® UNO Q, Arduino VENTUNO Q, Qualcomm Dragonwing™ IQ8 EVK, and Qualcomm Dragonwing IQ9 EVK platforms, illustrating how a common application architecture can scale from accessible development boards to professional Edge AI systems.

Rather than focusing only on inference, this session demonstrates the complete Edge AI development loop: collect data → train → package → deploy → run on real hardware → improve Attendees only need a smartphone to participate. All embedded hardware and live demonstrations are operated by the presenter.

What attendees will learn:

• How data for an embedded voice AI application can be collected collaboratively using smartphones
• How Edge Impulse simplifies dataset creation, training, and deployment for embedded AI
• How an AI model can be integrated into a containerized Embedded Linux application
• How Yocto, containers, AI runtimes, drivers, and hardware acceleration fit together
• What can remain portable across different embedded platforms and what stays hardware-specific
• How the same application architecture can scale from Arduino-class development boards to professional Edge AI platforms
• Why application/OS separation matters for updates and long-term product maintenance

No development board or laptop is required. Attendees will participate using their smartphones to contribute voice samples to the live dataset. All training, deployment, and embedded hardware interaction will be demonstrated live by the presenter.

Explore how NXP's FRDM automotive development platform, demonstrated with the FRDM-A-S32K344 board, helps engineers move quickly from concept to prototype. Through hands-on exercises, participants will work with S32K3 MCU capabilities, configure and validate applications using NXP software tools, and use FreeMASTER for real-time monitoring, visualization, and debugging. The workshop focuses on a practical workflow for faster prototyping, testing, and system optimization.

Relevant links: https://mcuxpresso.nxp.com/appcodehub?deviceFamily=s32k,s32m; https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-A-S32K344

In this 90-minute hands-on workshop, we will use LVGL Pro to build a modern UI for Riverdi's STM32U5 display board. We start with a short overview of LVGL Open, LVGL Pro, and LVGL Safe to see what they are used for and how they connect to form a complete UI ecosystem.

After that, in a longer hands-on session, we will create a project for the Riverdi board, take a design from Figma, import it into LVGL Pro, make some changes, and finally export the C code, compile it, and flash it to the board.

While using LVGL Pro, you will also gain hands-on experience with LVGL's declarative XML language. You will learn how to create reusable components, connect live data with bindings, add animations and translations, and more. At the end, you will know how to go from a design file to a running UI on real hardware in minutes and make changes with confidence.

Designing an FPGA-based system that works in the lab is only part of the challenge; creating a design that can be manufactured, deployed, and supported requires careful management of competing resource constraints. This 90-minute tutorial explores how FPGA resources, I/O allocation, power architecture, high-speed interfaces, PCB routing, component cost, and manufacturability influence system-level design decisions.

Using the open-source Adiuvo Explorer Board as a practical case study, the tutorial will show how requirements are translated into a resource budget and how engineering trade-offs are made when resources are limited.

Attendees will examine examples involving FPGA I/O and bank allocation, high-speed connectivity, configurable interface voltages, power management, PCB complexity, and cost targets. The session will provide a structured approach for identifying constraints early, evaluating architectural trade-offs, and making design decisions that lead to robust, manufacturable, and deployable FPGA systems.

This 90-minute workshop provides a practical introduction to SMARC carrier board development from a hardware designer’s perspective. Rather than focusing on interface specifications and signal definitions, the workshop highlights the design decisions that most frequently lead to project delays, redesigns, and bring-up challenges.

Using real-world examples, attendees will learn how to correctly interpret SMARC documentation, avoid common power-management mistakes, manage interface multiplexing, plan for future module migrations, and perform effective design reviews before PCB release.

The workshop is intended for hardware developers, system architects, and project engineers who are planning to create or review SMARC carrier board designs.

Key Takeaways:

• Understanding the responsibilities of the module and carrier board
• Avoiding common power and boot-related design issues
• Correctly selecting and implementing SMARC interfaces
• Reviewing layouts for high-risk design mistakes
• Designing carrier boards for future scalability and module migration

Discover how to accelerate the development of connected sensing applications using Amazon Sidewalk, the ST NUCLEO-WBA55CG wireless development board paired with the X-NUCLEO-IKS5A1 MEMS sensor expansion shield, and /IOTCONNECT. In this live session, you'll see how sensor data can be collected from edge devices, transmitted over Amazon Sidewalk's low-power network, and visualized through /IOTCONNECT for real-time monitoring and actionable insights. The solution demonstrates a streamlined approach to building secure, scalable IoT applications while reducing development complexity and time to deployment.

Learning objectives:

• Understand the role of Amazon Sidewalk in IoT connectivity and how its low-power, long-range network enables connected sensing applications.
• Configure and integrate the ST NUCLEO-WBA55CG development board and X-NUCLEO-IKS5A1 MEMS sensor shield to collect environmental and motion sensor data.
• Demonstrate how sensor data is transmitted from edge devices through Amazon Sidewalk to the cloud for monitoring and analysis.
• Utilize /IOTCONNECT to visualize device telemetry and create real-time monitoring dashboards that generate actionable insights from sensor data. Identify best practices for building secure, scalable IoT solutions that accelerate development and reduce time to deployment.

Join a hands-on workshop exploring Infineon DEEPCRAFT™ AI models running on the PSOC™ Edge E84 AI Evaluation Kit. All participants will be provided with a development kit to use during the workshop as you run edge AI use cases, explore sensor telemetry, and connect data to /IOTCONNECT powered by AWS for real-time dashboards and insights.

Learning Objectives:

• Build and deploy AI-powered edge applications using Infineon DEEPCRAFT™ AI models on the PSOC™ Edge E84 AI Evaluation Kit.
• Capture and analyze real-time sensor data from the development kit to enable intelligent sensing and decision-making at the edge.
• Evaluate practical edge AI use cases, including object detection, anomaly recognition, and sensor-based intelligence while running AI models locally on the device.
• Connect edge-generated data to /IOTCONNECT powered by AWS for secure cloud connectivity, device management, and telemetry streaming.
• Create real-time dashboards and visualizations that transform sensor data into actionable insights for monitoring, analytics, and business applications.

This Renesas workshop demonstrates an intelligent asset-tracking solution that uses an accelerometer and Reality AI to recognize movement events such as drops, shakes, and circular motion. The classified events are transmitted via Bluetooth Low Energy (BLE) to the Hubble network, enabling remote monitoring of an asset’s movement, handling, and exposure to major shocks.

Learning Objectives:

• Explore HW/SW assets for intelligent asset-tracking applications
• Use Renesas 365 to configure and implement a motion-recognition solution
• Build, deploy, and validate the application on Renesas hardware

Get hands-on with NXP's i.MX 95 FRDM development platform and explore its powerful feature set from the ground up. Connect a display, camera, and keyboard, launch real-world AI demos via GoPoint, and run applications on the Arm® Cortex®-A55 — all with minimal setup time.

Discover how the i.MX 95 accelerates product development while addressing modern demands for cybersecurity, power efficiency, and lifecycle management. Whether you design for industrial, automotive, smart city, or IoT applications, you will leave with practical insights to accelerate your next design-win.

Reinforcement learning is reshaping how robots learn to move. With recent breakthroughs at labs like ETH Zurich, Boston Dynamics, and Disney Research, walking robots are now handling rough terrain and challenges they were never explicitly trained for. The good news is that you don't need a fully equipped research lab to get started. In this hands-on workshop, participants will train an AI agent from scratch to balance a tiny wheeled robot, then watch it run on real hardware.

Using the MuJoCo physics simulator and Python, we'll build a complete RL training pipeline using the Proximal Policy Optimization (PPO) algorithm. We'll tackle two of the most common real-world challenges in robotics: how to make an agent that's actually robust (using domain randomization and curriculum learning)... and how to transfer a policy learned in simulation onto a physical robot (a problem known as the "sim-to-real" gap). By the end of the session, attendees will leave with hands-on intuition for modern robot learning.

Target Audience: Embedded developers and makers with some programming experience. No prior robotics or RL knowledge required, though familiarity with Python, Arduino, and basic ML concepts will help participants get the most out of the session.

The EU Cyber Resilience Act (CRA) marks a fundamental shift in how products with digital elements are designed, developed and maintained throughout their lifecycle. In this workshop, participants will gain a practical understanding of key CRA requirements and the engineering decisions needed to address them.

We will explore topics such as risk assessment, threat modeling, vulnerability management and lifecycle security, highlighting where security-by-design can help reduce complexity and accelerate CRA readiness. Using practical examples, we will discuss how NXP's security technologies, EdgeLock 2GO lifecycle management services and PSIRT (Product Security Incident Response Team) processes can support manufacturers in addressing key CRA requirements and preparing for long-term compliance.

Key Takeaways:

• Understand the role of security-by-design in addressing CRA requirements.
• Learn how risk assessment, threat modelling and vulnerability management contribute to CRA readiness.
• Discover how NXP's security portfolio, EdgeLock 2GO and PSIRT processes can help support key CRA requirements throughout the product lifecycle.

What changes when a familiar Raspberry Pi development platform becomes the basis of a product sold in the EU? Working from a defined example device and use case, participants will build a preliminary CRA requirements and evidence map. The exercise begins with a detailed use case analysis, and then moves to the manufacturer’s Article 13 risk assessment. We finish with comparing the tests design choices against Annex I: secure default configuration, protection from unauthorized access, confidentiality and integrity of data and software, security updates, and vulnerability handling.

The group will examine where Raspberry Pi documentation and standard software can help, including secure boot provisioning, disk encryption, image generation, software bills of materials, and security disclosures. It will also identify work that remains with the product manufacturer: defining the deployed configuration, securing exposed interfaces and credentials, managing keys, testing the complete system, documenting dependencies, and maintaining an update and response process over the support period.

The outcome is a practical set of dos and don’ts, open questions, and evidence requests that engineers can adapt to their own designs. The workshop will assess a hypothetical integration; it will not certify a Raspberry Pi product.

A system-on-module may be designed for secure operation, but its security properties only help an integrator when they can be configured, tested, documented, and maintained in the finished product. Using embeddedTS i.MX93 hardware as a working example, Marta Rybczynska and embeddedTS will examine what it takes to supply a component that supports a customer’s CRA assessment.

The session will trace the handoff from component to product: identifying the supplied hardware, firmware, and software; describing the boot chain and configurable security features; defining assumptions about the carrier board and operating environment; and specifying what the integrator must implement. It will connect those decisions to CRA risk assessment, product security and vulnerability handling requirements, and requirement to give integrators information needed for their own compliance work.

The example will also examine the operational handoff: software component records, vulnerability contacts, update responsibilities, support periods, and the evidence needed when a component changes. Attendees will leave with a concrete model for documenting security responsibilities across the supplier–integrator boundary.

Get hands-on with cellular IoT and security. In this interactive workshop, participants will receive an nRF9151 development kit and work step by step with our experts to secure a cellular IoT device using Exein Runtime for Zephyr. Together, we will explore the setup, configuration, and security options, giving you a practical experience.